INSTRUCTION AND INSTRUCTION SEQUENCING
The processor may perform a variety of functions and these are reflected in the variety of instructions defined for the processor. These instructions are also referred to as 'machine instructions' or 'computer instructions'.
Elements of an instruction:
Opcode : Specifies the operation to be performed
Example : ADD, SUB, etc
Source Operand : Input to an operation is specified in the source operand.
Destination Operand : Result of an operation is stored in the destination operand.
Operand address : Address of the operand (source operand or destination operand)
Instruction Representation :
The instructions can be represented using
i) Register Transfer Notation (RTN)
ii) Assembly Language Notation
i) Register Transfer Notation (RTN) : In this notation, the contents of a location are denoted by placing square brackets around the name of the location. The location may be memory address or processor register.
Example 1: R1 <- [LOC]
This expression means that the contents of memory location LOC are transferred into processor register R1.
Example 2: R3 <- [R1] + [R2]
This expression means that the contents of registers R1 and R2 are added and placed into the Register R3.
The right hand side of an RTN expression denotes a value and the left hand side is the name of the location.
ii) Assembly Language Notation:
In assembly language notation,
Basic Instruction Types:
The instructions can be classified
1) based on the nature of operation an instruction performs
2) based on the number of address fields an instruction has
Classification based on the nature of operation:
Based on the nature of operation an instruction performs, the instructions can be classified as:
Classification based on the number of address fields :
The number of addresses per instruction is a basic design decision for any instruction set architecture. Based on the number of address fields, the instruction can be classified as:
Three address Instruction : A three address instruction consists of two source operands and one destination operand. The general format for three address instruction is
Opcode Source1, Source2, Destination
Examples:
Instruction Register Transfer Notation
ADD A, B, C C <- [A] + [B]
SUB A, B, C C <- [A] - [B]
The number bits required to represent such instruction include the :
i) Bits required to specify the Opcode
ii) Bits required to specify the source and destination operands
Two address Instruction: In two address instruction, one of the two operands does a double duty as both source operand and destination operand. The general format for two address instruction is
Opcode Source1, Source2/Destination
Examples :
Instruction Register Transfer Notation
ADD A, B [B] <- [A] + [B]
In the above example, the content of B is overwritten. The number of bits required to represent such instruction is less compared to three address instruction.
One address instruction : One address instruction has one source operand field. The processor register 'Accumulator' is used as the other source operand and also as the destination operand. The general format for one address instruction is
Opcode Source1
Examples :
Instruction Register Transfer Notation
LOAD A Accumulator <- [A]
STORE B [B] <- [Accumulator]
SUB B [Accumulator] <- [Accumulator] -[B]
Zero address instruction : In zero address instruction, the locations of all operands are defined implicitly.
The general format for zero address instruction is
Opcode
Example:
POP
The instructions with one address requires less number of bits to represent it and instructions with three addresses require more number number of bits to represent it. Also, instruction with one address requires less memory access when compared to instructions with three address instruction. However using a processor with high wordlength, three address instructions can be handled efficiently.
Instruction Execution : To execute any program, it must be first loaded into the main memory and the Program Counter must point to the first instruction of the program. Basically, executing an intruction involves four phases : fetch - decode- execute- write result
Instruction Execution Cycle
The execution flow may be either in sequence or it may branch.
Straight line Sequencing : In straight line sequencing, the instructions are executed one-by-one by the processor in the order of increasing addresses. In otherwords, the Program Counter is incremented uniformly.
Example : A straight line sequencing program for C <- [A] + [B]
Branching : In branching, the instructions are not executed in the order of increasing addresses but the execution branches to a different location specified in the branch instruction. Branch instructions allows to branch to a different set of instructions either conditionally or unconditionally. The branch instructions have a target address that specifies the location where the execution should be moved to.
A conditional branch instruction causes a branch only if a specified condition is satisfied. If the condition is not satisfied, the PC (Program Counter) is incremented in the normal way.
Example for branching:
Condition Codes:
The condition code flags are used to store the result of certain condition when certain operations are performed. The condition code flags are stored in status register(also called flag register).
Some of the common condition code flags are :
Condition Code Flag Description
Negative (N) - Set to 1 if the result is negative; else 0
Zero (Z) - Set to 1 if the result is zero; else 0
Overflow(V) - Set to 1 if arithmetic overflow occurs; else 0
Carry(C) - Set to 1 if carry-out results from the operation; else 0
Generating Memory addresses
The address of the memory can be specified directly within the instruction.
Example: MOVE [2000H], R1
There are situations when we need to change the memory address dynamically, especially in case of loops
The processor may perform a variety of functions and these are reflected in the variety of instructions defined for the processor. These instructions are also referred to as 'machine instructions' or 'computer instructions'.
Elements of an instruction:
Opcode : Specifies the operation to be performed
Example : ADD, SUB, etc
Source Operand : Input to an operation is specified in the source operand.
Destination Operand : Result of an operation is stored in the destination operand.
Operand address : Address of the operand (source operand or destination operand)
Instruction Representation :
The instructions can be represented using
i) Register Transfer Notation (RTN)
ii) Assembly Language Notation
i) Register Transfer Notation (RTN) : In this notation, the contents of a location are denoted by placing square brackets around the name of the location. The location may be memory address or processor register.
Example 1: R1 <- [LOC]
This expression means that the contents of memory location LOC are transferred into processor register R1.
Example 2: R3 <- [R1] + [R2]
This expression means that the contents of registers R1 and R2 are added and placed into the Register R3.
The right hand side of an RTN expression denotes a value and the left hand side is the name of the location.
ii) Assembly Language Notation:
In assembly language notation,
- Opcodes are represented by mnemonics that indicate operations like ADD, SUB, etc.
- Operands are represented by symbols that indicate data. The operands may indicate address, numbers, characters and logical data.
Opcode
|
Operand
|
Operand
|
Basic Instruction Types:
The instructions can be classified
1) based on the nature of operation an instruction performs
2) based on the number of address fields an instruction has
Classification based on the nature of operation:
Based on the nature of operation an instruction performs, the instructions can be classified as:
- Data movement instructions e.g. : MOVE, LOAD, STORE
- I/O control instructions e.g. : IN, OUT
- Arithmetic and logic instruction e.g. : ADD, SUB, NOT, OR, AND
- Program sequencing and control instructions e.g.: JUMP, LOOP, RETURN
Classification based on the number of address fields :
The number of addresses per instruction is a basic design decision for any instruction set architecture. Based on the number of address fields, the instruction can be classified as:
- Three address Instruction : Has three operand fields
- Two address Instruction : Has two operand fields
- One address Instruction : Has one operand field
- Zero address Instruction : Has no operand field
Three address Instruction : A three address instruction consists of two source operands and one destination operand. The general format for three address instruction is
Opcode Source1, Source2, Destination
Examples:
Instruction Register Transfer Notation
ADD A, B, C C <- [A] + [B]
SUB A, B, C C <- [A] - [B]
The number bits required to represent such instruction include the :
i) Bits required to specify the Opcode
ii) Bits required to specify the source and destination operands
Two address Instruction: In two address instruction, one of the two operands does a double duty as both source operand and destination operand. The general format for two address instruction is
Opcode Source1, Source2/Destination
Examples :
Instruction Register Transfer Notation
ADD A, B [B] <- [A] + [B]
In the above example, the content of B is overwritten. The number of bits required to represent such instruction is less compared to three address instruction.
One address instruction : One address instruction has one source operand field. The processor register 'Accumulator' is used as the other source operand and also as the destination operand. The general format for one address instruction is
Opcode Source1
Examples :
Instruction Register Transfer Notation
LOAD A Accumulator <- [A]
STORE B [B] <- [Accumulator]
SUB B [Accumulator] <- [Accumulator] -[B]
Zero address instruction : In zero address instruction, the locations of all operands are defined implicitly.
The general format for zero address instruction is
Opcode
Example:
POP
The instructions with one address requires less number of bits to represent it and instructions with three addresses require more number number of bits to represent it. Also, instruction with one address requires less memory access when compared to instructions with three address instruction. However using a processor with high wordlength, three address instructions can be handled efficiently.
Instruction Execution : To execute any program, it must be first loaded into the main memory and the Program Counter must point to the first instruction of the program. Basically, executing an intruction involves four phases : fetch - decode- execute- write result
Instruction Execution Cycle
The execution flow may be either in sequence or it may branch.
Straight line Sequencing : In straight line sequencing, the instructions are executed one-by-one by the processor in the order of increasing addresses. In otherwords, the Program Counter is incremented uniformly.
Example : A straight line sequencing program for C <- [A] + [B]
Branching : In branching, the instructions are not executed in the order of increasing addresses but the execution branches to a different location specified in the branch instruction. Branch instructions allows to branch to a different set of instructions either conditionally or unconditionally. The branch instructions have a target address that specifies the location where the execution should be moved to.
A conditional branch instruction causes a branch only if a specified condition is satisfied. If the condition is not satisfied, the PC (Program Counter) is incremented in the normal way.
Example for branching:
Condition Codes:
The condition code flags are used to store the result of certain condition when certain operations are performed. The condition code flags are stored in status register(also called flag register).
Some of the common condition code flags are :
Condition Code Flag Description
Negative (N) - Set to 1 if the result is negative; else 0
Zero (Z) - Set to 1 if the result is zero; else 0
Overflow(V) - Set to 1 if arithmetic overflow occurs; else 0
Carry(C) - Set to 1 if carry-out results from the operation; else 0
Generating Memory addresses
The address of the memory can be specified directly within the instruction.
Example: MOVE [2000H], R1
There are situations when we need to change the memory address dynamically, especially in case of loops
