Assignments and Notes

Hi all ! Hope you all enjoyed your pongal holidays well. I have the assignments at : Click it http://assignmentsincoa.blogspot.in/.

All the best ! Please inform your friends also. Contribute your assignments to complete our syllabus for Unit I.

UNIT I : BASIC STRUCTURE OF COMPUTERS 

Click the links to read the notes

Functional units – Basic operational concepts – Bus structures – Performance and metrics – Instructions and instruction sequencing – Hardware – Software Interface – Instruction set architecture – Addressing modes - RISC-CISC. ALU design – Fixed point and floating point operations.

Problem Sets
Two marks

RISC - CISC

RISC – CISC

Introduction

The Instruction Set Architecture of a processor defines the various functions that the processor can perform.  The design of a processor and its instruction set architecture are closely related. Depending on the design of the processor, its instruction set may have different opcodes, addressing modes, instruction formats, instruction length and so on. 

It is based on the Instruction Set Architecture of a particular processor, the high level language instructions are converted into its corresponding machine instructions.

Defining RISC and CISC :

The term RISC and CISC refers to the design principles and techniques of a processor.

•  Defining RISC-CISC in terms of processor design

 The RISC processors have simple design (usually LOAD/STORE architecture) whereas CISC processors are complicated design(Memory-Memory or Register-Memory Architecture).  RISC is hardwired controlled whereas CISC is microprogram controlled.

•  Defining RISC-CISC in terms of Instruction Set Architecture

RISC(Reduced Instruction Set Computer) have simple instructions, so the average cycles per instruction (CPI) is less usually 1. However, the compiled program (object code) has more lines of code, hence requires more RAM. Since CPI is less, RISC enables efficient pipelining.

RISC

CISC(Complex Instruction Set Computer) have complex instructions, so the average CPI is high(usually 2 to 15). However, the compiled program has few lines of code, hence requires less RAM. Pipelining cannot be efficiently implemented since CPI is high.

Performance Equation

The performance equation is given by

Execution time= Instruction count x CPI x Clock period

(or)

Execution time= ( N x S ) / R

For RISC, instruction count (N) is high and CPI is less. So pipelining can be done efficiently.

For CISC, instruction count (N) is less and CPI is high. Pipelining is not as efficient as RISC.

RISC and CISC : A Comparison

The architectural distinction between RISC and CISC is shown below:

 

RISC architecture uses separate instruction and data caches. Their access paths are also different. CISC processor uses a unified cache for both data and instructions; hence uses the same path.

Mostly the RISC processors are hardwired controlled whereas the CISC processors are microprogammed control. Hence control memory is needed in these processors.

A summarized comparison of RISC and CISC

 

RISC	CISC
Simple Processor design	Complicated Processor design
Uses Load-Store architecture(also called the Register- Register architecture )	Uses Memory-Memory or Register-Memory architectures
RISC is hardwired controlled	CISC is microprogram-controlled
Uses simple instructions	Uses powerful, complex instructions
More lines of code in the object code	Less number of lines in the object code
Requires more memory and more instruction fetch	Requires less memory and less instruction fetch compared to RISC
The average cycles per instruction is less (usually 1)	The average cycles per instruction is high (usually 2 to 15)
Highly Pipelined	Pipelining is not as efficient as CISC
Uses fixed length instructions	Uses variable length instructions
Adressing mode is simple	Large variety of addressing modes
Uses large number of register sets	Less number of registers
Memory reference is less. Only LOAD, STORE instructions refer memory	Most of the instructions refer memory (LOAD and STORE incorporated in the instruction itself)